Additive bit-serial algorithm for discrete logarithm modulo 2k

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Additive bit-serial algorithm for discrete logarithm modulo 2k

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A novel algorithm for computing the discrete logarithm modulo 2k that is suitable for fast software or hardware implementation is described. The chosen preferred implementation is based on a linear-time multiplier-less method and has a critical path of less than k modulo 2k shift-and-add operations.

Inspec keywords: digital arithmetic; mathematics computing

Other keywords: linear time multiplier less method; hardware implementation; shift and add operations; fast software implementation; discrete logarithm modulo 2k; additive bit serial algorithm; critical path; k modulo 2k shift operation

Subjects: Mathematics computing; Digital arithmetic methods

References

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      • N.S. Szabo , R.I. Tanaka . (1967) Residue arithmetic and its applications to computer technology.
    2. 2)
      • Fit-Florea, A., Matula, D.W.: `A digit-serial algorithm for the discrete logarithm modulo 2', IEEE 15th Int. Conf. on Application-Specific Systems, Architectures and Processors, 2004, ASAP.
    3. 3)
      • I. Niven , H.S. Zuckerman . (1966) An introduction to the theory of numbers.
    4. 4)
      • Benschop, N.F.: `Multiplier for the multiplication of at least two figures in an original format', US, 5,923,888, 13 July 1999.
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