The twin SONOS memory (TSM) transistors for 2-bit/cell non-volatile-memory (NVM) application are presented and their reliability is evaluated so that they can be applied to next generation NVM technology. This new memory, which is implemented by the damascene gate and outer sidewall spacer processes, shows a high reliability down to 80 nm gate length.
References
-
-
1)
-
E. Lusky ,
Y. Shacham-Diamand ,
G. Mitenberg ,
A. Shappir ,
I. Bloom ,
B. Eitan
.
Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices.
IEEE Trans. Electron Devices
,
3 ,
444 -
451
-
2)
-
B. Eitan ,
P. Pavan ,
I. Bloom ,
A. Efraim ,
A. Frommer ,
D. Finzi
.
NROM: a novel localized trapping, 2-bit nonvolatile memory cell.
IEEE Electron Device Lett.
,
11 ,
543 -
545
-
3)
-
M.H. White ,
Y. Yang ,
A. Purwar ,
M.L. French
.
A low voltage SONOS nonvolatile semiconductor memory technology.
IEEE Trans. Compon. Packag. Manuf. Technol.
,
2 ,
190 -
195
-
4)
-
Fukuda, M., Nakanishi, T., Nara, Y.: `Scaled 2 bit/cell SONOS type nonvolatile memory technology for sub-90 nm embedded application using SiN sidewall trapping structure', Tech. Dig. Int. Electron Devices Mtg, December 2003, Washington, DC, USA, p. 909–912.
-
5)
-
Y.K. Lee ,
K.W. Song ,
J.W. Hyun ,
J.D. Lee ,
B.-G. Park ,
S.T. Kang ,
J.D. Choe ,
S.Y. Han ,
J.N. Han ,
S.W. Lee ,
O.I. Kwon ,
C. Chung ,
D. Park ,
K. Kim
.
Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process.
IEEE Electron Device Lett.
,
5 ,
317 -
319
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