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Linearisation of MOS resistors using capacitive gate voltage averaging

Linearisation of MOS resistors using capacitive gate voltage averaging

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A compact implementation of a scheme to improve linearity of MOS resistors is introduced. It is based on capacitive gate voltage averaging in conjunction with large resistive biasing elements implemented using MOS transistors operating in subthreshold. Experimental results from a test chip in 0.5 µm CMOS technology are shown that verify the proposed technique.

Inspec keywords: CMOS integrated circuits; linearisation techniques; MIS devices; resistors

Other keywords: capacitive gate voltage averaging; resistive biasing elements; MOS resistors; 0.5 micron; MOS transistor; CMOS technology

Subjects: Metal-insulator-semiconductor structures; Semiconductor devices; CMOS integrated circuits; Resistors

References

    1. 1)
      • M. Bikumandla , J. Ramírez-Angulo , C. Urquidi , R.G. Carvajal , A.J. López-Martín . Biasing CMOS amplifiers using MOS transistors in subthreshold region. IEICE Electronics Express , 12 , 339 - 345
    2. 2)
      • R. Gregorian , G.C. Temes . (1986) Analog MOS integrated circuits and signal processing.
    3. 3)
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    5. 5)
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