Accurate sample-and-hold circuit model

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Accurate sample-and-hold circuit model

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Published

An accurate circuit model is presented for the general sample-and-hold circuit with a finite sampling duration. The applications of the model, such as to design a direct down-conversion sampler (RF sampler) and to calculate the thermal noise and output SNR of the general sample-and-hold circuit, are discussed. The results provide a theoretical basis for understanding and designing a sample-and-hold circuit.

Inspec keywords: circuit noise; sample and hold circuits; network synthesis

Other keywords: sample-and-hold circuit model; direct down-conversion sampler; RF sampler; finite sampling duration; thermal noise

Subjects: Other analogue circuits

References

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      • Yuan, J.: `Accurate sampling of radio signals beyond GHz in CMOS', GHz2000 Symp., March 2000, p. 277–280.
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      • Razavi, B.: `Design of sample-and-hold amplifiers for high-speed low-voltage a/d converters', Proc. IEEE Custom Integrated Circuits Conf., May 1997, p. 59–66.
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