Verification was sought for the memory operation of a single transistor type ferroelectric random access memory (1T type FeRAM) with a circuit model for a memory cell transistor combined with a precharged capacitive decoupling sensing scheme. The wiring scheme of the 1T type FeRAM array was also proposed based on the operation of the fabricated memory cell transistor. As a result, the memory operation of 1T type FeRAM was confirmed at a low current level with high sensing speed and no reference cell, and the design and verification of the full chip were achieved.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el_20046555
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