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Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports

Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports

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A proposal to improve the low access bandwidth of conventional one-port caches by utilising a multi-bank structure with distributed crossbar to increase port number at small additional area cost is presented. This enables combination of data and instruction caches into a single multi-port cache as well as different wordlength for each port. Through dynamically scheduling the storage space used for data and instructions, 25% smaller storage capacity is sufficient for a given maximum cache-miss probability.

References

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      • Fukae, S., Omori, N., Mattausch, H.J., Koide, T., Inoue, T., Hironaka, T.: `Optimized bank-based multi-port memories through a hierarchical multi-bank structure', Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), 2003, p. 323–330.
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      • H.J. Mattausch , K. Kishi , T. Gyoten . Area-efficient multiport SRAMs for on-chip data-storage with high random access bandwidth and large storage capacity. IEICE Trans. Electron. , 37 , 410 - 417
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      • Burger, D., Austin, T.: `The SimpleScalar tool set Version 2.0', 1342, Tech., 1997.
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