Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

50 Gbit/s 2:1 multiplexer in 0.13 µm CMOS technology

50 Gbit/s 2:1 multiplexer in 0.13 µm CMOS technology

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© IEE
Published

A fully integrated 2:1 multiplexer IC which operates at up to 50 Gbit/s data rate is presented. The MUX uses inductive shunt peaking and an output series inductor for higher bandwidth. The MUX directly drives the 50 Ω load. The IC is fabricated in a 0.13 µm bulk CMOS technology and draws 65 mA at 1.5 V supply voltage. The output voltage swing is 2×100 mV.

Inspec keywords: integrated optics; CMOS integrated circuits; multiplexing equipment

Other keywords: output series inductor; 0.13 μm CMOS technology; 50 Gbit/s; 65 mA; 50 Gbit/s 2:1 multiplexer; 50 ohm; 0.13 micron; 1.5 V; inductive shunt peaking

Subjects: CMOS integrated circuits; Integrated optics; Multiplexing and switching in optical communication

References

    1. 1)
      • Vadipour, M., Savoj, J.: `A low-power 20-Gb/s 2:1 multiplexer/driver', European Solid-State Circuit Conf., 2002, Firenze, Italy, p. 231–234.
    2. 2)
      • Knapp, H., Wohlmuth, H.D., Wurzer, M., Rest, M.: `25 GHz static frequency divider and 25 Gb/s multiplexer in 0.12 µm CMOS', IEEE Int. Solid-State Circuits Conf., 2002, p. 302–303.
    3. 3)
      • D. Kehrer , H.D. Wohlmuth , H. Knapp , M. Wurzer , A.L. Scholtz . 40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120 nm standard CMOS. IEEE J. Solid-State Circuits , 11 , 1830 - 1837
    4. 4)
      • Wohlmuth, H.D., Kehrer, D.: `A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS', European Solid-State Circuits Conf., 2002, Firenze, Italy, p. 823–826.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20040090
Loading

Related content

content/journals/10.1049/el_20040090
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address