A new FRAM design method utilising the bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by on-pitch plate control circuitry. It also reduces the power consumption in memory array. Implementation results for a 0.13 µm, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of the conventional structure.
References
-
-
1)
-
Kang, H.-B.: `A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on 1T1C FeRAM', Symp. on VLSI Circuits Dig. Tech. Pprs, June 2001, Orlando, FL, USA, p. 125–126.
-
2)
-
M.-K. Choi
.
A 0.25-µm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme.
IEEE J. Solid-State Circuits
,
1472 -
1478
-
3)
-
R. Ogiwara
.
A 0.5-µm, 3-V, 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor.
IEEE J. Solid-State Circuits
,
545 -
551
-
4)
-
Y. Chung ,
B.-G. Jeon ,
K.-D. Suh
.
A 3.3-V 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme.
IEEE J. Solid-State Circuits
,
697 -
704
-
5)
-
Sumi, T.: `A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns', Proc. ISSCC, February 1994, San Francisco, CA, USA, p. 268–269.
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