Your browser does not support JavaScript!

FRAM design style utilising bit-plate parallel cell architecture

FRAM design style utilising bit-plate parallel cell architecture

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A new FRAM design method utilising the bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by on-pitch plate control circuitry. It also reduces the power consumption in memory array. Implementation results for a 0.13 µm, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of the conventional structure.


    1. 1)
      • Kang, H.-B.: `A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on 1T1C FeRAM', Symp. on VLSI Circuits Dig. Tech. Pprs, June 2001, Orlando, FL, USA, p. 125–126.
    2. 2)
    3. 3)
    4. 4)
    5. 5)
      • Sumi, T.: `A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns', Proc. ISSCC, February 1994, San Francisco, CA, USA, p. 268–269.

Related content

This is a required field
Please enter a valid email address