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FRAM design style utilising bit-plate parallel cell architecture

FRAM design style utilising bit-plate parallel cell architecture

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A new FRAM design method utilising the bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by on-pitch plate control circuitry. It also reduces the power consumption in memory array. Implementation results for a 0.13 µm, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of the conventional structure.

References

    1. 1)
      • Sumi, T.: `A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns', Proc. ISSCC, February 1994, San Francisco, CA, USA, p. 268–269.
    2. 2)
    3. 3)
    4. 4)
      • Kang, H.-B.: `A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on 1T1C FeRAM', Symp. on VLSI Circuits Dig. Tech. Pprs, June 2001, Orlando, FL, USA, p. 125–126.
    5. 5)
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