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STI/LOCOS compatible LDMOS structure in standard CMOS

STI/LOCOS compatible LDMOS structure in standard CMOS

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A novel high-voltage transistor structure compatible with shallow trench isolation and local oxidation of silicon is described. This device, which can be implemented in a standard CMOS process, is capable of handling high voltages without destruction. A duplication of the breakdown voltage was measured.

Inspec keywords: isolation technology; power MOSFET; oxidation; CMOS integrated circuits; semiconductor device breakdown

Other keywords: breakdown voltage; STI; LDMOS structure; CMOS process; LOCOS; high-voltage transistor

Subjects: Insulated gate field effect transistors; Surface treatment (semiconductor technology); CMOS integrated circuits; Power semiconductor devices

References

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      • Annema, A.-J., Geelen, G., de Jong, P.: `5.5 V tolerant I/O in a 2.5 V 0.25 µm CMOS technology', Proceedings Custom Integrated Circuits Conference, 2000, Orlanda, FL, USA, p. 417–420.
    2. 2)
      • 't Eynde, F.O., Zorio, C.: `An EEPROM in a standard CMOS technology', Proceedings European Solid-State Circuits Conference, 1997, Southampton, UK, p. 264–267.
    3. 3)
      • Z. Parpia , C.A.T. Salama , R.A. Hadaway . Modeling and characterization of CMOS-compatible high-voltage device structures. IEEE Trans. Electron Devices , 11 , 2335 - 2343
    4. 4)
      • A.S. Grove , O. Leistiko , W.W. Hooper . Effect of surface fields on the breakdown voltage of planar silicon p–n junctions. IEEE Trans. Electron Devices , 3 , 157 - 162
    5. 5)
      • J. Kim , S.-G. Kim , T.M. Roh , H.S. Park , J.-G. Koo , D.Y. Kim . Characteristics of P-channel SOI LDMOS transistor with tapered field oxides. ETRI J. , 3 , 22 - 28
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