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Solution to trapped charge in FGMOS transistors

Solution to trapped charge in FGMOS transistors

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A solution to the problem of charge being trapped on the gate of a floating gate MOS transistor during fabrication is presented. The solution does not alter the floating nature of the gate of the device since it does not use any kind of active or passive device to get rid of the accumulated charge. In addition, it does not require any post-processing techniques such as exposure to UV light and does not require any extra masks.

Inspec keywords: MOSFET; electric charge; MOS integrated circuits; integrated circuit layout

Other keywords: layout technique; floating gate MOS transistor; trapped charge; accumulated charge removal; fabrication; FGMOS transistors

Subjects: Insulated gate field effect transistors; Other MOS integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing

References

    1. 1)
    2. 2)
      • Rodriguez-Villegas, E.: `Low voltage and low power analog and digital design with the floating gate MOS transistor (FGMOS)', 2002, PhD, University of Seville, Spain.
    3. 3)
      • E. Rodriguez-Villegas , A. Yufera , A. Rueda . A 1.25 V micropower Gm-C FGMOS filter in weak inversion. IEEE J. Solid-State Circuits
    4. 4)
      • Hasler, P.: `Foundations of learning in analog VLSI', 1997, PhD, California Institute of Technology, Pasadena, CA, USA.
    5. 5)
      • Lai, S.: `Flash memories: where we were and where we are going', Proc. IEEE Int. Electron Devices Mtg, 1998, San Francisco, CA, USA, p. 971–974.
    6. 6)
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