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Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.
Inspec keywords: tunnelling magnetoresistance; magnetoresistive devices; cache storage; random-access storage
Other keywords:
Subjects: Memory circuits; Magneto-acoustic, magnetoresistive, magnetostrictive and magnetostatic wave devices; Storage on stationary magnetic media