High cell-efficiency synchronous MRAM adopting unified bit-line cache

Access Full Text

High cell-efficiency synchronous MRAM adopting unified bit-line cache

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© IEE
Published

Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.

Inspec keywords: tunnelling magnetoresistance; magnetoresistive devices; cache storage; random-access storage

Other keywords: random access memory; unified bit-line cache; low-latency column operations; synchronous magnetoresistive RAM; magnetic-tunnel junction cell; high-speed column operation; high cell-efficiency MRAM

Subjects: Memory circuits; Magneto-acoustic, magnetoresistive, magnetostrictive and magnetostatic wave devices; Storage on stationary magnetic media

References

    1. 1)
      • Motoyoshi, M., Moriyama, K., Mori, H., Fukumoto, C., Itoh, H., Kano, H., Bessho, K., Narisawa, H.: `High-performance MRAM technology with an improved magnetic tunnel junction material', Dig. Tech. Pr., IEEE Symp. on VLSI Technology, 2002, Honolulu, HI, USA, p. 212–213.
    2. 2)
      • Naji, P.K., Durlam, M., Tehrani, S., Calder, J., DeHerrera, M.F.: `A 256 kb 3.0 V 1T1MTJ nonvolatile magnetoresistive RAM', IEEE Int. Solid-State Circuits Conf., 2001, San Francisco, CA, USA, p. 122–123.
    3. 3)
      • Yamada, K., Sakai, N., Ishizuka, Y., Mameno, K.: `A novel sensing scheme for a MRAM with a 5% MR ratio', Dig. Tech. Pr., IEEE Symp. on VLSI Technology, 2001, Kyoto, Japan, p. 123–124.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20030783
Loading

Related content

content/journals/10.1049/el_20030783
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading