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High cell-efficiency synchronous MRAM adopting unified bit-line cache

High cell-efficiency synchronous MRAM adopting unified bit-line cache

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Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.

References

    1. 1)
      • Naji, P.K., Durlam, M., Tehrani, S., Calder, J., DeHerrera, M.F.: `A 256 kb 3.0 V 1T1MTJ nonvolatile magnetoresistive RAM', IEEE Int. Solid-State Circuits Conf., 2001, San Francisco, CA, USA, p. 122–123.
    2. 2)
      • Motoyoshi, M., Moriyama, K., Mori, H., Fukumoto, C., Itoh, H., Kano, H., Bessho, K., Narisawa, H.: `High-performance MRAM technology with an improved magnetic tunnel junction material', Dig. Tech. Pr., IEEE Symp. on VLSI Technology, 2002, Honolulu, HI, USA, p. 212–213.
    3. 3)
      • Yamada, K., Sakai, N., Ishizuka, Y., Mameno, K.: `A novel sensing scheme for a MRAM with a 5% MR ratio', Dig. Tech. Pr., IEEE Symp. on VLSI Technology, 2001, Kyoto, Japan, p. 123–124.
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