For access to this article, please select a purchase option:
IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.
Your recommendation has been sent to your librarian.
A 4-bit, 2.5 V modified flash analogue-to-digital converter (ADC) has been designed. In this design, the new flash topology only requires 2(N−2)+2 comparators. For comparison reasons, this new ADC architecture is operated at 400 MHz, consumes a total power of 1.68 mW and generates a total noise power of 4.86×10−15 · Δf (V2) at this frequency.
Inspec keywords: analogue-digital conversion; integrated circuit noise; comparators (circuits)
Other keywords:
Subjects: A/D and D/A convertors; A/D and D/A convertors