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An open-loop clock deskewing circuit for high-speed synchronous DRAM

An open-loop clock deskewing circuit for high-speed synchronous DRAM

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An open-loop clock deskewing circuit (CDC) for high-speed synchronous DRAM is described. Unlike the conventional circuits, the CDC does not require an additional measure delay line, thus power consumption is reduced. The delay is measured directly from the main delay line and both the input and output ports of the delay line are movable. The CDC provides a deskewed clock within two clock cycles.

References

    1. 1)
      • Saeki, T., Minami, K., Yoshida, H., Suzuki, H.: `The direct skew detect synchronous mirror delay (direct SMD) for ASICs', Proc. IEEE Custom Integrated Circuits Conf., 1998, Santa Clara, CA, USA, p. 511–514.
    2. 2)
      • Han, J.-M., Lee, J.-B., Yoon, S.-S., Jeong, S.-J., Park, C., Cho, I.-J., Lee, S.-H., Seo, D.-I.: `Skew minimization techniques for 256M-bit synchronous DRAM and beyond', Digest of Technical Papers, IEEE Symposium on VLSI Circuits, 1996, p. 192–193.
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