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Design of dividable interleaver for parallel decoding in turbo codes

Design of dividable interleaver for parallel decoding in turbo codes

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A dividable interleaving method is proposed for turbo codes with parallel architecture to achieve high-throughput. This method not only solves the memory conflict problem in extrinsic information memory, but reduces the required memory for the interleaver. Many kinds of interleaver type are applicable to this method, the BER performance is similar to that achieved by other interleavers.

References

    1. 1)
      • Berrou, C., Glavieux, A., Thitimajshima, P.: `Near Shannon limit error-correcting coding and decoding: turbo-codes', IEEE Int. Conf. on Communications, May 1993, Geneva, Switzerland, 2, p. 1064–1070
    2. 2)
      • Schurgers, C., Catthoor, F., Engels, M.: `Optimized MAP turbo decoder', IEEE Workshop on Signal Processing Systems, 2000, Lafayette, LA, USA, p. 245–254
    3. 3)
      • Hsu, J.-M., Wang, C.-L.: `A parallel decoding scheme for turbo codes', IEEE Int. Symp. on Circuits and Systems, June 1998, Monterey, CA, USA, 4, p. 445–448
    4. 4)
      • Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements.
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