Design of dividable interleaver for parallel decoding in turbo codes

Design of dividable interleaver for parallel decoding in turbo codes

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A dividable interleaving method is proposed for turbo codes with parallel architecture to achieve high-throughput. This method not only solves the memory conflict problem in extrinsic information memory, but reduces the required memory for the interleaver. Many kinds of interleaver type are applicable to this method, the BER performance is similar to that achieved by other interleavers.


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