Nonmonotone norm-reduction method for circuit simulation

Nonmonotone norm-reduction method for circuit simulation

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A nonmonotone norm-reduction method for aiding the convergence of Newton–Raphson iteration is presented. The simulation results with some benchmark circuits show that a nonmonotone norm-reduction method may reduce the number of line searches during the iteration.


    1. 1)
      • H.R. Yeager , R.W. Dutton . Improvement in norm-reducing Newton methods for circuit simulation. IEEE Trans. Comput. Aided Des. , 5 , 538 - 546
    2. 2)
      • L. Grippo , F. Lampariello , S. Lucidi . A nonmonotone line search technique for Newton's method. SIAM J. Numer. Anal. , 4 , 707 - 716
    3. 3)
      • M. Ferris , S. Lucidi , M. Roma . Nonmonotone curvilinear line search method for unconstrained optimization. Comput. Optim. Appl. , 117 - 136
    4. 4)
      • M. Valtonen , P. Heikkilä , H. Jokinen , T. Veijola , G.A.S. Machado . (1996) APLAC – object-oriented circuit simulator and design tool, Low-power HF microelectronics: a unified approach.
    5. 5)

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