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Steady-state error minimisation technique for single-phase PWM inverters

Steady-state error minimisation technique for single-phase PWM inverters

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A steady-state error minimisation technique of a single-phase pulse-width modulated (PWM) inverter is presented. This technique employs a phase-locked loop concept utilising the phase difference between the capacitor voltage and current, which is similar to the dq transform of three phase variables. The experimental results are provided to show the effectiveness.

References

    1. 1)
      • N.M. Abdel-Rahim , J.E. Quaicoe . Analysis and design of a multiple feedback loop control strategy for single-phase voltage-source UPS inverters. IEEE Trans. Power Electron. , 4 , 532 - 541
    2. 2)
      • S.-L. Jung , Y.-Y. Tzou . Discrete sliding-mode control of a PWM inverter for sinusoidal output waveform synthesis with optimal sliding curve. IEEE Trans. Power Electron. , 4 , 567 - 577
    3. 3)
      • M.J. Ryan , W.E. Brumsickle , R.D. Lorenz . Control topology options for single-phase UPS inverter. IEEE Trans. Ind. Appl. , 2 , 493 - 501
    4. 4)
      • K.P. Gokhale , A. Kawamura , R.G. Hoft . Dead beat microprocessor control of PWM inverter for sinusoidal output waveform synthesis. IEEE Trans. Ind. Appl. , 6 , 901 - 910
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