Steady-state error minimisation technique for single-phase PWM inverters

Steady-state error minimisation technique for single-phase PWM inverters

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A steady-state error minimisation technique of a single-phase pulse-width modulated (PWM) inverter is presented. This technique employs a phase-locked loop concept utilising the phase difference between the capacitor voltage and current, which is similar to the dq transform of three phase variables. The experimental results are provided to show the effectiveness.


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