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Fast locking delay-locked loop using initial delay measurement

Fast locking delay-locked loop using initial delay measurement

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© IEE
Published

A delay-locked loop (DLL) architecture capable of incorporating fast locking and low jitter features simultaneously is reported. A test chip was fabricated in a 0.6 µm CMOS process to prove its functionality. The proposed DLL can align the internal clock to the external reference clock within two cycles and maintain its locking state with the aid of feedback operation.

Inspec keywords: circuit feedback; clocks; delay lock loops; CMOS digital integrated circuits; timing jitter

Other keywords: feedback operation; fast locking delay-locked loop; internal clock alignment; 0.6 micron; register controlled DLL; synchronous mirror DLL; external reference clock; delay-locked loop architecture; CMOS process; double-poly double-metal CMOS technology; low jitter; locking state maintenance; initial delay measurement; test chip

Subjects: Other digital circuits; CMOS integrated circuits

References

    1. 1)
      • Y. Okajima . Digital delay locked loop and design technique for high-speed synchronous interface, special issue on ULSI Memory Technology. IEICE Trans. Electron. , 6 , 798 - 807
    2. 2)
      • T. Saeki , Y. Nakaoka , M. Fujita , A. Tanaka . A 2.5-ns clock access, 250 MHZ, 256 Mb SDRAM with synchronous mirror delay. IEEE J. Solid-State Circuits , 1656 - 1668
    3. 3)
      • Garlepp, B.W.: `A portable digital DLL architecture for CMOS interface circuits', Symp. on VLSI Circuits Dig. Tech. Papers, 1998, Honolulu, Hawaii, p. 214–215.
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