http://iet.metastore.ingenta.com
1887

Clock distribution scheme for high-speed DRAM

Clock distribution scheme for high-speed DRAM

For access to this article, please select a purchase option:

Buy article PDF
$19.95
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A novel clock distribution scheme is proposed for high-speed DRAM to minimise clock-skew among data buffers. It has ideally zero-skew characteristic by employing folded clock lines and phase blending circuits. Simulation results show that the maximum clock-skew between two receivers located 4 mm apart is less than 20 ps, regardless of process, voltage, and temperature variations.

References

    1. 1)
      • P.J. Restle , T.G. Mcnamara , D.A. Webber , P.J. Camporese , K.F. Eng , K.A. Jenkins , D.H. Allen , M.J. Rohn , M.P. Quaranta , D.W. Boerstler , C.J. Alpert , C.A. Carter , R.N. Bailey , J.G. Petrovick , B.L. Krauter , B.D. Mccredie . A clock distribution network for microprocessors. IEEE J. Solid-State Circuits , 5 , 792 - 799
    2. 2)
      • A. Boni , A. Pierazzi , D. Vecchi . LVDS I/O interface for Gb/s-per-pin operation in 0.35-µm CMOS. IEEE J. Solid-State Circuits , 4 , 706 - 711
    3. 3)
      • M. Bazes . Two novel fully complementary self-biased CMOS differential amplifiers. IEEE J. Solid-State Circuits , 2 , 165 - 168
    4. 4)
      • B.W. Garlepp , K.S. Donnelly , J. Kim , P.S. Chau , J.L. Zerbe , C. Huang , C.V. Tran , C.L. Portmann , D. Stark , Y.F. Chan , T.H. Lee , M.A. Horowitz . A portable digital DLL for high-speed CMOS interface circuits. IEEE J. Solid-State Circuits , 5 , 632 - 644
    5. 5)
      • Wee, J.K., Kim, Y.H., Kim, Y.J., Lee, P.S., Jeon, Y.J., Kim, J.H., Yoon, H.S., Chung, J.Y.: `A study of underlayer geometry effects on interconnect line characteristics through S-parameter measurements', Proc. Electronic Components Technology Conf., May 2001, Orlando, FL, USA, p. 1290–1294.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20020446
Loading

Related content

content/journals/10.1049/el_20020446
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address