Clock distribution scheme for high-speed DRAM

Clock distribution scheme for high-speed DRAM

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A novel clock distribution scheme is proposed for high-speed DRAM to minimise clock-skew among data buffers. It has ideally zero-skew characteristic by employing folded clock lines and phase blending circuits. Simulation results show that the maximum clock-skew between two receivers located 4 mm apart is less than 20 ps, regardless of process, voltage, and temperature variations.


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