Defect dependent memory switching in amorphous silicon alloys
Defect dependent memory switching in amorphous silicon alloys
- Author(s): J.M. Shannon ; R.G. Gateru ; E.G. Gerstner
- DOI: 10.1049/el:20020160
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- Author(s): J.M. Shannon 1 ; R.G. Gateru 1 ; E.G. Gerstner 1
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View affiliations
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Affiliations:
1: School of Electronics, Computing and Mathematics, University of Surrey, Guildford, Surrey, United Kingdom
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Affiliations:
1: School of Electronics, Computing and Mathematics, University of Surrey, Guildford, Surrey, United Kingdom
- Source:
Volume 38, Issue 5,
28 February 2002,
p.
249 – 250
DOI: 10.1049/el:20020160 , Print ISSN 0013-5194, Online ISSN 1350-911X
It is shown that memory switching in amorphous silicon alloys is affected by ion bombardment. In particular, ion damage lowers the voltage required to form devices and switch them into the on-state. This technique enables optimised non-volatile memory devices to be made with improved switching ratios.
Inspec keywords: semiconductor storage; wide band gap semiconductors; metal-semiconductor-metal structures; electrical conductivity transitions; hydrogen; amorphous semiconductors; silicon compounds; ion beam effects
Other keywords:
Subjects: Electrical properties of metal-semiconductor-metal structures; Metal-insulator transitions and other electronic transitions; Radiation effects (semiconductor technology); Metal-insulator-metal and metal-semiconductor-metal structures; Ion beam effects; Memory circuits
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