Bit-wise read-compare-write scheme for low power read-modify-write DRAM operation

Access Full Text

Bit-wise read-compare-write scheme for low power read-modify-write DRAM operation

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© IEE
Published

To save power consumption in read-modify-write (RMW) DRAM operation, a bit-wise read-compare-write (RCW) scheme is presented. Its power consumption depends on the number of bits that have to be updated by the bit-wise compare result between the read data and the modified data. If a random bit-wise update ratio is assumed, a 11.6% power saving is achieved when the proposed scheme is applied to the previous design.

Inspec keywords: integrated circuit design; low-power electronics; DRAM chips; logic design

Other keywords: power saving; bit-wise compare result; bit updating; low power read-modify-write DRAM operation; bit-wise read-compare-write scheme; read data; power consumption; random bit-wise update ratio; DRAM design; read-modify-write DRAM operation; modified data

Subjects: Memory circuits; Semiconductor storage; Digital circuit design, modelling and testing; Semiconductor integrated circuit design, layout, modelling and testing; Logic design methods

References

    1. 1)
      • Y.-H. Park , S.-H. Han , J.-H. Lee , H.-J. Yoo . A 7.1 GB/s low power rendering engine in 2D array embedded memory logic CMOS for portable multimedia system. IEEE J. Solid-State Circuits , 6 , 944 - 955
    2. 2)
      • K. Inoue , H. Nakamura , H. Kawai . A 10 Mb frame buffer memory with Z-compare and A-blend units. IEEE J. Solid-State Circuits , 12 , 1563 - 1568
    3. 3)
      • Kook, J., Yoo, H.-J.: `A single bit line writing scheme for low power reconfigurable I/O DRAM macro', IEEE European Solid-State Circuit Conference of Digest of Technical Paper, September 2000, p. 420–423.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20020069
Loading

Related content

content/journals/10.1049/el_20020069
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading