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CMOS implementation of all-analogue APP decoders: analysis of performances and limitations

CMOS implementation of all-analogue APP decoders: analysis of performances and limitations

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The potential performances and limitations of an all-analogue implementation of a posteriori-probability (APP) decoders in a standard complementary-metal-oxide semiconductor (CMOS) technology are investigated. In particular, the accuracy and speed trade-off related to the usage of MOS transistors in the weak inversion (w.i.) region is analysed in depth. Transistor level simulations of a (18, 9, 5) tail-biting decoder are reported and contrasted with the results of the software implementation of the same decoding algorithm.

References

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      • Loeliger, H.-A., Lustenberger, F., Helfenstein, M., Tarköy, F.: `Probability propagation and decoding in analog VLSI', Proc. Int. Symp. Information Theory, 1998, Cambridge, MA, USA, p. 146.
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      • Berrou, C., Glavieux, A., Thitimajshima, P.: `Near Shannon limit error-correcting coding and decoding: turbo-codes', Proc. IEEE Int. Conf. Communication, May 1993, Geneva, Switzerland, p. 1064–1070.
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      • Hagenauer, J., Winkelhofer, M.: `The analog decoder', Proc. Int. Symp. Information Theory, 1998, Cambridge, MA, USA, p. 145.
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