Low power, high speed, charge recycling CMOS threshold logic gate

Low power, high speed, charge recycling CMOS threshold logic gate

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.


    1. 1)
      • K. Kotani , T. Shibata , M. Imai , T. Ohmi . Clocked-neuron-MOS logic circuits employing auto-threshold-adjustment. Dig. Tech. Pap. IEEE Int. Solid-State Circuits Conf. , 320 - 321
    2. 2)
      • Huang, H.Y., Wang, T.N.: `CMOS capacitor coupling logic (C', Proc. IEEE Asia Pacific Conf. ASIC, 2000, p. 33–36.
    3. 3)
      • M.J. Avedillo , J.M. Quintana , A. Rueda , E. Jiménez . Low-power CMOS threshold-logic gate. Electron. Lett. , 25 , 2157 - 2159
    4. 4)
      • S. Muroga . (1971) Threshold logic and its applications.
    5. 5)
      • B.S. Kong , J.D. Im , Y.C. Kim , S.J. Jang , Y.H. Jun . Asynchronous sense differential logic. Dig. Tech. Pap. IEEE Int. Solid-State Circuits Conf. , 284 - 285

Related content

This is a required field
Please enter a valid email address