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Low power, high speed, charge recycling CMOS threshold logic gate

Low power, high speed, charge recycling CMOS threshold logic gate

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A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.

References

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      • Huang, H.Y., Wang, T.N.: `CMOS capacitor coupling logic (C', Proc. IEEE Asia Pacific Conf. ASIC, 2000, p. 33–36.
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      • S. Muroga . (1971) Threshold logic and its applications.
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      • B.S. Kong , J.D. Im , Y.C. Kim , S.J. Jang , Y.H. Jun . Asynchronous sense differential logic. Dig. Tech. Pap. IEEE Int. Solid-State Circuits Conf. , 284 - 285
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