ASMD with duty cycle correction scheme for high-speed DRAM

Access Full Text

ASMD with duty cycle correction scheme for high-speed DRAM

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© IEE
Published

An analogue synchronous mirror delay with duty cycle correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range.

Inspec keywords: high-speed integrated circuits; circuit simulation; DRAM chips; clocks; synchronisation; analogue processing circuits; delays

Other keywords: analogue synchronous mirror delay; ASMD; dual edge triggering systems; clock synchronisation; half value current source; high-speed DRAM; wide duty cycle range; simulation results; duty cycle-correction scheme; internal clock duty cycle stabilisation

Subjects: Memory circuits; Semiconductor storage; Analogue processing circuits; Storage system design

References

    1. 1)
      • T. Saeki , K. Koyama , T. Okubo . A 2.5-ns clock access, 250 MHz, 256-Mb SDRAM withsynchronous mirror delay. IEEE J. Solid-State Circuits , 1656 - 1665
    2. 2)
      • J. Chae , D. Kim . Wide range single-way-pumping synchronous mirror delay. Electron. Lett. , 939 - 940
    3. 3)
      • D. Shim , D. Lee , S. Jung , C. Kim , W. Kim . An analog synchronous mirror delay for high-speedDRAM application. IEEE J. Solid-State Circuits , 484 - 493
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20010717
Loading

Related content

content/journals/10.1049/el_20010717
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading