Instruction cache organisation for embedded low-power processors

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Instruction cache organisation for embedded low-power processors

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A low-power I-cache architecture is proposed that is appropriate for embedded low-power processors. Unlike existing schemes, the proposed organisation places an extra small cache in parallel alongside the L1 cache. Since it allows simultaneous accesses to both caches, the proposed scheme introduces little performance degradation. Using simple hardware logic (for sequential accesses) and a compiler transformation (for loop accesses), most L1 cache requests are served by a small cache, so that the amount of energy consumed by the L1 cache is significantly reduced. Experimental results show that for the SPEC95 benchmarks, the proposed organisation reduces the energy-delay product on average by 67.2% over a conventional cache design and 16.8% over the filter cache design.

Inspec keywords: memory architecture; cache storage; low-power electronics; microprocessor chips

Other keywords: embedded low-power processors; L1 cache; loop accesses; instruction cache organisation; hardware logic; compiler transformation; energy-delay product reduction; low-power I-cache architecture; sequential accesses

Subjects: Memory circuits; Storage system design; Microprocessor chips; Semiconductor storage; Microprocessors and microcomputers

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      • N. Bellas , I. Hajj , C. Polychropoulos , G. Stamoulis . Architectural and compiler techniques for energy reduction in high-performancemicroprocessors. IEEE Trans. VLSI Syst. , 3 , 317 - 326
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      • Wilton, S.E., Jouppi, N.: `An enhanced access and cycle time model for on-chip caches', DEC WRL, Technical report, 1994.
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      • Kin, J., Gupta, M., Mangione-Smith, W.H.: `The filter cache: an energy efficient memory structure', Proc. Int. Symp. Microarchitecture, 1997, p. 45–49.
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