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Optimisation for improved short-channel performance of surrounding/cylindrical gate MOSFETs

Optimisation for improved short-channel performance of surrounding/cylindrical gate MOSFETs

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A new technique is proposed to optimise the device parameters of a thin-film fully depleted SGT MOSFET to minimise short-channel effects. The model offers new opportunities for realising future ULSI circuits with SGTs.

References

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      • R.H. Yan , A. Qurmazd , K.F. Lee . Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Devices , 7 , 1704 - 1710
    2. 2)
      • T. Endoh , T. Nakamura , F. Masuoka . An analytical steady-state current-voltage characteristics of short channelfully depleted surrounding gatetransistor (FD-SGT). IEICE Trans. Electron. , 7 , 911 - 917
    3. 3)
      • K.N. Ratnakumar , J.D. Meindl . Short channel MOST threshold voltage model. IEEE J. Solid-State Circuits , 5 , 937 - 947
    4. 4)
      • C.P. Auth , J.D. Plummer . Scaling theory for cylindrical fully-depleted, surrounding gate MOSFETs. IEEE Electron Device Lett. , 2 , 74 - 76
    5. 5)
      • H. Takato , K. Sunouchi , N. Okabe , A. Nitayama , K. Hieda , F. Horiguchi , F. Masuoka . Impact of surrounding gate transistor (SGT)for ultra high density LSIs. IEEE Trans. Electron Devices , 3 , 573 - 578
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