CMOS limiting amplifier for SDH STM-16 optical receiver

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CMOS limiting amplifier for SDH STM-16 optical receiver

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Published

A 2.5 Gbit/s limiting amplifier is realised in a 0.35 µm CMOS technology. At a supply voltage of 5 V, the power dissipation is 225 mW. The input dynamic range is about 40 dB at a constant output voltage swing (400 mVp-p). The chip area is 1 × 1.1 mm2.

Inspec keywords: synchronous digital hierarchy; optical fibre communication; optical limiters; CMOS analogue integrated circuits; optical receivers; wideband amplifiers

Other keywords: wideband amplifiers; SDH STM-16 optical receiver; 225 mW; supply voltage; CMOS limiting amplifier; power dissipation; 2.5 Gbit/s; constant output voltage swing; input dynamic range; 5 V; optical fibre links; 0.35 micron

Subjects: Optical communication equipment; CMOS integrated circuits; Amplifiers; Multiplexing and switching in optical communication; Optical fibre networks

References

    1. 1)
      • M. Moller , H.M. Rein , H. Wernz . 13 Gb/s Si-bipolar AGC amplifier IC with high gain and wide dynamic rangefor optical-fiber receivers. IEEE J. Solid-State Circuits , 7 , 815 - 822
    2. 2)
      • M. Fukaishi , K. Nakamura , M. Sato , Y. Tsutsui , S. Kishi , M. Yotsuyanagi . A 4.25 Gb/s fiber channel transceiver with asynchronous tree-type demultiplexerand frequency conversion architecture. IEEE J. Solid-State Circuits , 12 , 2139 - 2147
    3. 3)
      • Wang, Zhi-Gong, Berroth, M., Hurm, V., Lang, M., Nowotny, U., Hofmann, P., Hulsmann, A., Kohler, K., Raynor, B., Schneider, : `17 GHz-bandwidth 17 dB-gain 0.3 µm-HEMT low-power limiting amplifier', 1995 Symp. VLSI Circuits, Dig. Tech. Papers, p. 97–98.
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