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Efficient back-bias voltage generator with suppressed parasitic bipolar action for low-voltage DRAMs

Efficient back-bias voltage generator with suppressed parasitic bipolar action for low-voltage DRAMs

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Published

A high-efficiency back-bias voltage generator with cross-coupled hybrid pumping circuit (CHPC2) is presented. This scheme suppresses the parasitic bipolar turning-on so as not to lose the pumping current into the parasitic npn bipolar transistor. The proposed generator exhibits better efficiency and faster pumping speed compared with previous bipolar-suppressed back-bias voltage generators.

Inspec keywords: DRAM chips; low-power electronics; CMOS memory circuits

Other keywords: LV dynamic RAM; high-efficiency voltage generator; back-bias voltage generator; parasitic bipolar action suppression; cross-coupled hybrid pumping circuit; parasitic n-p-n bipolar transistor; low voltage DRAMs

Subjects: Memory circuits; CMOS integrated circuits; Semiconductor storage

References

    1. 1)
      • P. Favrat , P. Deval , M. Declercq . A high-efficiency CMOS voltage doubler. IEEE J. Solid-State Circuits , 3 , 410 - 416
    2. 2)
      • Kyeong-Sik Min . Efficient back-bias generator with cross-coupled hybridpumping circuit for sub-1.5 V DRAMs. Electron. Lett. , 7 , 613 - 615
    3. 3)
      • Y. Tsukikawa , T. Kajimoto , Y. Okasaka , Y. Morooka , K. Furutani , H. Miyamoto , H. Ozaki . An efficient back-bias generator with hybrid pumping circuit for 1.5-VDRAM's. IEEE J. Solid-State Circuits , 4 , 534 - 538
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20010047
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