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Modified super pass gate for multiple-valued logic circuits

Modified super pass gate for multiple-valued logic circuits

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A model of a super pass gate (SPG) is adapted to allow multiple-valued logic circuit connections and designs that are normally prohibited by the formal synthesis and minimisation technique for the device. The modification of the SPG allows more efficient circuit minimisation to be achieved for functions that do not readily reduce under the formal synthesis technique.

References

    1. 1)
      • A. Gonzalez . Multiple-valued signed-digit adder using negative differential-resistancedevices. IEEE Trans. Comput. , 9 , 947 - 959
    2. 2)
      • X. Deng , T. Hanyu , M. Kamayama . Synthesis of multiple-valued logic networks based on super pass gates. Multi. Val. Logic , 161 - 183
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20001288
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