Bit line sensing strategy for testing for data retention faults in CMOS SRAMs

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Bit line sensing strategy for testing for data retention faults in CMOS SRAMs

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A strategy for testing for data retention faults in CMOS static random access memories (SRAMs) is proposed. Sensing the voltage at one of the data bus lines with a proper design for testability (DFT) reading circuitry enables the fault-free memory cells from any defective cell(s) to be determined. DFT reading circuitry is also proposed. An analysis of the cost of the proposed approach in terms of area, test time and performance degradation is presented.

Inspec keywords: design for testability; fault location; CMOS memory circuits; integrated circuit testing; SRAM chips

Other keywords: CMOS SRAM; data bus lines; DFT reading circuitry; static random access memories; bit line sensing strategy; data retention faults; design for testability; static RAM testing

Subjects: Other aspects of storage devices and techniques; Digital circuit design, modelling and testing; Memory circuits; Logic design methods; Semiconductor integrated circuit design, layout, modelling and testing; Semiconductor storage; CMOS integrated circuits

References

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      • C. Kuo , T. Toms , B.T. Neel , J. Jelemensky , E. Carter , P. Smith . Soft-defect detection (SDD) technique for a high-reliability CMOS SRAM. IEEE J. Solid-State Circuits , 61 - 67
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      • R. Dekker , F. Beenker , L. Thijssen . A realistic fault model and test algorithms for static random accessmemories. IEEE Trans. , 6 , 567 - 572
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      • V.H. Champac , J. Castillejos , J. Figueras . IDDQ testing of opens in CMOS SRAMs. J. Electron. Test. (JETTA) , 53 - 62
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      • Meixner, A., Banik, J.: `Weak write test mode: An SRAM cell stability design for test technique', Int. Test Conf., 1996, p. 309–318.
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