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Bit line sensing strategy for testing for data retention faults in CMOS SRAMs

Bit line sensing strategy for testing for data retention faults in CMOS SRAMs

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A strategy for testing for data retention faults in CMOS static random access memories (SRAMs) is proposed. Sensing the voltage at one of the data bus lines with a proper design for testability (DFT) reading circuitry enables the fault-free memory cells from any defective cell(s) to be determined. DFT reading circuitry is also proposed. An analysis of the cost of the proposed approach in terms of area, test time and performance degradation is presented.


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