Column redundancy scheme for multiple I/O DRAM using mapping table

Access Full Text

Column redundancy scheme for multiple I/O DRAM using mapping table

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© IEE
Published

A new column redundancy scheme is presented that can minimise the die area overhead by repair circuits and also achieve fast access speed in high density dynamic random access memories (DRAMs) with wide data widths. The proposed scheme has a large redundancy-area-unit (RAU) which operates a flexible column redundancy scheme that consecutively shifts RDQ (redundant I/O) to neighbouring MDQ (main I/O) without any speed penalty. By using the proposed mapping fuse algorithm, the number of fuses required to store the fail bit address can be reduced, and the chip area reduced.

Inspec keywords: DRAM chips; redundancy; integrated circuit reliability

Other keywords: die area overhead; dynamic random access memories; wide data widths; mapping table; multiple I/O DRAM; dynamic RAM; chip area reduction; high density DRAM; repair circuits; column redundancy scheme; fast access speed; mapping fuse algorithm; redundancy-area-unit

Subjects: Reliability; Semiconductor integrated circuits; Semiconductor storage; Maintenance and reliability; Memory circuits

References

    1. 1)
      • C. Kim . A 2.5V, 72-Mbit, 2.0-Gbyte/s packet-based DRAM with a 1.0-Gbps/pin interface. IEEE J. Solid-State Circuits , 5 , 645 - 652
    2. 2)
      • S. Takase . A 1.6-Gbyte/s DRAM with flexible mapping redundancy technique and additionalrefresh scheme. IEEE J. Solid-State Circuits , 11 , 1600 - 1606
    3. 3)
      • Namekawa, : `Dynamically shift-switched dataline redundancy suitable for DRAM macrowith wide data bus', Symp. VLSI Circuits, June 1999, p. 149–152.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20000712
Loading

Related content

content/journals/10.1049/el_20000712
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading