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Column redundancy scheme for multiple I/O DRAM using mapping table

Column redundancy scheme for multiple I/O DRAM using mapping table

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A new column redundancy scheme is presented that can minimise the die area overhead by repair circuits and also achieve fast access speed in high density dynamic random access memories (DRAMs) with wide data widths. The proposed scheme has a large redundancy-area-unit (RAU) which operates a flexible column redundancy scheme that consecutively shifts RDQ (redundant I/O) to neighbouring MDQ (main I/O) without any speed penalty. By using the proposed mapping fuse algorithm, the number of fuses required to store the fail bit address can be reduced, and the chip area reduced.

References

    1. 1)
      • C. Kim . A 2.5V, 72-Mbit, 2.0-Gbyte/s packet-based DRAM with a 1.0-Gbps/pin interface. IEEE J. Solid-State Circuits , 5 , 645 - 652
    2. 2)
      • Namekawa, : `Dynamically shift-switched dataline redundancy suitable for DRAM macrowith wide data bus', Symp. VLSI Circuits, June 1999, p. 149–152.
    3. 3)
      • S. Takase . A 1.6-Gbyte/s DRAM with flexible mapping redundancy technique and additionalrefresh scheme. IEEE J. Solid-State Circuits , 11 , 1600 - 1606
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