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Fast quadratic increase of multiport-storage-cell area with port number

Fast quadratic increase of multiport-storage-cell area with port number

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It is shown that the space required for wordline/bitline routing leads to a quadratic multiport-storage-cell area increase with port number N, dominating from as little as N = 2, N = 6 for small ROM and large SRAM cell types, respectively. Larger N results in enormous area increases (e.g. by a factor of 80 for a 32-port SRAM), making conventional multiport memories unacceptable for most practical applications.

References

    1. 1)
      • H.J. Mattausch , K. Yamada . Application of port-access-rejection probability theory for integratedN-port memory architecture optimisation. Electron. Lett. , 861 - 862
    2. 2)
      • Crisp, R., Donnelly, K., Moncayo, A., Perino, D., Zerbe, J.: `Development of single-chip multi-GB/s DRAMs', ISSCC Dig. Tech. Papers, 1997, p. 226–227.
    3. 3)
      • H.J. Mattausch . Hierarchical architecture for area-efficient N-port memories with latency-freemulti-Gbit/s access bandwidth. Electron. Lett. , 1441 - 1443
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