Fast quadratic increase of multiport-storage-cell area with port number

Fast quadratic increase of multiport-storage-cell area with port number

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for $120.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

It is shown that the space required for wordline/bitline routing leads to a quadratic multiport-storage-cell area increase with port number N, dominating from as little as N = 2, N = 6 for small ROM and large SRAM cell types, respectively. Larger N results in enormous area increases (e.g. by a factor of 80 for a 32-port SRAM), making conventional multiport memories unacceptable for most practical applications.


    1. 1)
      • Crisp, R., Donnelly, K., Moncayo, A., Perino, D., Zerbe, J.: `Development of single-chip multi-GB/s DRAMs', ISSCC Dig. Tech. Papers, 1997, p. 226–227.
    2. 2)
      • H.J. Mattausch . Hierarchical architecture for area-efficient N-port memories with latency-freemulti-Gbit/s access bandwidth. Electron. Lett. , 1441 - 1443
    3. 3)
      • H.J. Mattausch , K. Yamada . Application of port-access-rejection probability theory for integratedN-port memory architecture optimisation. Electron. Lett. , 861 - 862

Related content

This is a required field
Please enter a valid email address