Implementation of high speed Viterbi detectors

Access Full Text

Implementation of high speed Viterbi detectors

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

The normal Viterbi architecture and a radix 4 architecture are compared with a parallel ACS version using a latch based storage element. Results obtained using an eight-state EPR4 Viterbi detector show that parallel ACS architectures can provide a high level of performance with modest area requirements.

Inspec keywords: disc drives; partial response channels; hard discs; Viterbi detection

Other keywords: disk drive storage; high speed Viterbi detectors; area requirements; eight-state EPR4 Viterbi detector; latch based storage element; radix 4 architecture; Viterbi architecture; parallel ACS version

Subjects: Signal detection; Storage on moving magnetic media; Signal processing theory; Magnetic recording

References

    1. 1)
      • G.D. Forney . Maximum-likelihood sequence estimation of digital sequences in the presenceof intersymbol interference. IEEE Trans. , 363 - 378
    2. 2)
      • H.K. Thapar , A.M. Patel . A class of partial response systems for increasing storage density inmagnetic recording. IEEE Trans. , 5 , 3666 - 3668
    3. 3)
      • Fettweis, G.P., Karabed, R., Seigel, P., Thapar, H.: `Method and means for detecting partial response waveforms using a modifieddynamic programming heuristic', United States, 5,430,744, 4 July 1995.
    4. 4)
      • A.P. Hekstra . An alternative to metric rescaling in Viterbi decoders. IEEE Trans. , 11 , 1220 - 1222
    5. 5)
      • P.J. Black , T.H. Meng . A 140-Mb/s, 32-state, radix-4 Viterbi decoder. IEEE J. Solid-State Circuits , 1877 - 1885
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19991413
Loading

Related content

content/journals/10.1049/el_19991413
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading