Low voltage CMOS full adder cells

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Low voltage CMOS full adder cells

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A formal design procedure for realising a minimal transistor CMOS XOR-XNOR cell using pass networks is presented that successfully scales down with power supply voltage and fully compensates for the threshold voltage drop in MOS transistors. A full adder using this cell is also presented.

Inspec keywords: logic gates; adders; integrated circuit design; low-power electronics; logic design; CMOS logic circuits

Other keywords: LV CMOS full adder cells; CMOS XOR-XNOR cell; pass networks; low voltage cells; minimal transistor CMOS cell; formal design procedure; power supply voltage; threshold voltage drop compensation

Subjects: Digital circuit design, modelling and testing; Logic circuits; Semiconductor integrated circuit design, layout, modelling and testing; Logic and switching circuits; Logic design methods; CMOS integrated circuits; Semiconductor logic elements

References

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      • N. Weste , K. Eshraghian . (1993) Principles of CMOS VLSI design, a systems perspective.
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      • J. Wang , S. Fang , W. Feng . New efficient designs for XOR and XNOR functions on the transistor level. IEEE J. Solid-State Circuits , 7 , 780 - 786
    3. 3)
      • Shams, A.M., Bayoumi, M.A.: `A new full adder cell for low-power applications', Proc. IEEE Great Lakes Symp. VLSI, 1998, p. 45–49.
    4. 4)
      • D. Radhakrishnan . Design of CMOS circuits. IEE Proc. Circuits Devices Syst. , 1 , 83 - 90
    5. 5)
      • Radhakrishnan, D.: `The design and analysis of pass transistor switching circuits', 1983, PhD, University of Idaho, Moscow, Idaho, USA.
    6. 6)
      • Lee, H., Sobelman, G.E.: `New low-voltage circuits for XOR and XNOR', Proc. IEEE Southeastcon, 1997, p. 225–229.
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