Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

25.6 Gbit/s horizontally and vertically accessible embedded multiport SRAM

25.6 Gbit/s horizontally and vertically accessible embedded multiport SRAM

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© IEE
Published

An architecture for an embedded 8-port SRAM with 256 bit simultaneous horizontal and vertical data access for adjacent or alternate addresses is proposed. This architecture makes possible four kinds of address configurations which are effective in video applications by selecting multiple word lines and one of four bit lines for each column multiplexer. The proposed SRAM provides 25.6 Gbit/s of high bandwidth.

Inspec keywords: multiport networks; multiplexing equipment; SRAM chips; memory architecture

Other keywords: architecture; video applications; embedded multiport SRAM; column multiplexer; horizontal data access; multiple word lines; vertical data access; address configurations; 25.6 Gbit/s; 256 bit

Subjects: Semiconductor storage; Memory circuits

References

    1. 1)
      • P. Pirsch , H. Stolberg . VLSI implementation of image and video multimedia processing systems. IEEE Trans. Circuits Syst. Video Technol. , 7 , 878 - 891
    2. 2)
      • A. Silburt , R. Phillips , G. Gibson , P. Diedrich . A 180-MHz 0.8-µm BiCMOS modular memory family of DRAM and multiportSRAM. IEEE J. Solid-State Circuits , 3 , 222 - 231
    3. 3)
      • Chen, L., Jiu, J., Chang, H., Lee, Y., Ku, C.: `Low power 2D DCT chip design for wireless multimedia terminals', IEEE Int. Symp. Circuits and Systems, 1998, 4, p. 41–44.
    4. 4)
      • T. Masaki , Y. Morimoto , T. Onoye , I. Shirakawa . VLSI implementation of IDCT and motion compensator for MPEG2 HDTV videodecoding. IEEE Trans. Circuits Syst. Video Technol. , 5 , 387 - 395
    5. 5)
      • S. Dutta , W. Wolf , A. Wolfe . A methodology to evaluate memory architecture design tradeoffs for videosignal processors. IEEE Trans. Circuits Syst. Video Technol. , 1 , 36 - 53
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19991248
Loading

Related content

content/journals/10.1049/el_19991248
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address