While existing datapath compilers generate the same size buffer for all bits, in real datapaths, the load capacitance fluctuates according to the bit position, which leads to a nonuniform bit delay with unnecessarily high power consumption. This Letter proposes a datapath layout compiler using a bit-wise cell sizing scheme that reduces the power consumption by equalising the delay of each bit position to the critical bit delay. Experimental results using the example of a real microprocessor have demonstrated a power consumption saving using the tri-state bus of 12% on average, compared to conventional datapaths using a uniform-size cell.
References
-
-
1)
-
Chuang, W., Hajj, I.N.: `Delay area optimization for compact placement by gate resizing and relocation', Proc. ICCAD, 1994, p. 145–148.
-
2)
-
D.A. Joy ,
M.J. Cieslelski
.
Clock period minimization with wave-pipelining.
IEEE Trans.
,
4 ,
461 -
472
-
3)
-
Kyong, C.M., Park, I.C., Hong, S.K., Kong, H.S., Seong, K.S.: `HK386: an x86-compatible 32bit CISC microprocessor', Proc. ASP-DAC '97, 1997, p. 661–662.
-
4)
-
Y. Tsujihashi ,
H. Matsumoto ,
H. Nishimaki ,
Nako Nako ,
O. Kitada ,
S. Iwada ,
S. Kayano ,
M. Sakao
.
A high-density data-path generator with stretchable cells.
IEEE JSSC
,
1 ,
2 -
7
-
5)
-
Cai, H., Note, S., Six, P., De Man, H.: `A data path layout assembler for high performance DSP circuits', Proc. 27th DAC, 1990, p. 306–311.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19991236
Related content
content/journals/10.1049/el_19991236
pub_keyword,iet_inspecKeyword,pub_concept
6
6