A fast lock-on time mixed mode delay locked loop (DLL) is proposed to eliminate phase error in two steps. A digital fixed delay line compensates for the initial large phase error and an analogue voltage controlled delay line compensates for the small static phase error, resulting in low jitter. The lock-on time of the DLL is less than 10 clock cycles and the simulated jitter is below 10 ps at 200 MHz.
References
-
-
1)
-
S. Takanori ,
N. Yuji
.
A 2.5 ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirrordelay.
IEEE J. Solid-State Circuits
,
11 ,
1656 -
1665
-
2)
-
Atsushi, H., Hirohiko, M.: `A 256 Mb SDRAM using a register-controlled digital DLL', ISSCC Dig. Tech. Papers, 1997, p. 72–73.
-
3)
-
Jang, S.-J., Han, S.-H., Yoo, H.-J.: `A compact ring delay line for low power high speed synchronous DRAM', Symp. VLSI Circuits, 1998, p. 60–61.
-
4)
-
C.-H. Kim ,
J.-B. Lee
.
A 64-Mbit, 640-Mbyte/s bidirectional data strobed, double-data-rate SDRAMwith a 40-mW DLL for a256-Mbyte memory system.
IEEE J. Solid-State Circuits
,
11 ,
1703 -
1710
-
5)
-
J.G. Maneatis
.
Low-jitter process-independent DLL and PLL based on self-biased techniques.
IEEE J. Solid-State Circuits
,
11 ,
1723 -
1732
-
6)
-
I.A. Young ,
J.K. Greason ,
J.E. Smith ,
K.-L. Wong
.
A PLL clock generator with 5 to 110 MHz of lock range for microprocessor.
IEEE J. Solid-State Circuits
,
11 ,
1599 -
1607
-
7)
-
S. Stefanos
.
A semidigital dual delay-locked loop.
IEEE J. Solid-State Circuits
,
11 ,
1683 -
1692
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19991217
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