Hierarchical architecture for area-efficient integrated N-port memories with latency-free multi-gigabit per second access bandwidth

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Hierarchical architecture for area-efficient integrated N-port memories with latency-free multi-gigabit per second access bandwidth

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A two-level hierarchy is exploited for an area-efficient integrated N-port memory architecture, based on 1-port memory cells. The architecture is applicable to all types of dynamic, static and nonvolatile memory. It allows simultaneous read/write access from all ports, with access-rejection probability adjustable to application needs.

Inspec keywords: memory architecture; integrated memory circuits

Other keywords: two-level hierarchy; dynamic memory; memory architecture; 1-port memory cells; adjustable access-rejection probability; static memory; novolatile memory; hierarchical architecture; multi-gigabit per second access bandwidth; simultaneous read/write access; latency-free multi-Gbit/s access bandwidth; area-efficient integrated N-port memories

Subjects: Storage system design; Memory circuits; Semiconductor storage

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