An architecture for direct hardware implementation of programmable ternary de Bruijn sequence generators is described. The approach employed is based on the use of two recently introduced ternary logic components: the J3K3 flip-flop sequencer and the hybrid implemented U-gate. Generation of de Bruijn sequences and the proposed implementation approach are described with the aid of an example.
References
-
-
1)
-
J.J. Blakley ,
J.A.C. Webb ,
S.J. Laverty
.
Three-level m-sequence generation using ternary hybrid U-gateand JRKR flip-flop logic primitives.
Int. J. Electron.
,
605 -
613
-
2)
-
J.A.C. Webb ,
S.J. Laverty
.
Extension of the T-gate concept to a hybrid U-gate architecture for ternaryand higher order logic systems.
Electron. Lett.
,
1629 -
1630
-
3)
-
Beale, M., Cochrane, S.D., Lau, S.M.S.: `A programmable de Bruijn sequence generator for stream ciphers', Proc. 2nd Int. Conf. on IEE-Secure Communication Systems, 1986, p. 69–73.
-
4)
-
J.A.C. Webb ,
S.M.N. Forbes ,
J. Wilson ,
S.J. Laverty
.
Hybrid higher radix JK flip-flop sequencer with ASIC implementation potential.
Electron. Lett.
,
1933 -
1935
-
5)
-
A. Ralston
.
De Bruijn sequences - A model example of the interaction of discretemathematics and computer science.
Math. Mag.
,
131 -
143
-
6)
-
S. Xie
.
Notes on de Bruijn sequences.
Discrete Appl. Math.
,
157 -
177
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19981693
Related content
content/journals/10.1049/el_19981693
pub_keyword,iet_inspecKeyword,pub_concept
6
6