The architecture of a shared multibuffer ATM switch that uses the cyclic address queue method is described. No memory speedup is required. The blocking effect is eliminated for unicast traffic. Multicast functions are efficiently carried out via a multicast queue. A dynamic multicast scheme is used to improve the unfairness problem.
References
-
-
1)
-
S. Kumar ,
D.P. Agrawal
.
On multicast support for shared-memory-based ATM switch architecture.
IEEE Netw.
,
34 -
39
-
2)
-
E.W. Zegura
.
Architectures for ATM switching systems.
IEEE Commun. Mag.
-
3)
-
Lin, Y.-S., Shung, C.B.: `Queue management for shared buffer and shared multi-buffer ATM switches', Proc. IEEE INFOCOM, 1996, p. 688–695.
-
4)
-
H. Kondoh ,
H. Notani ,
H. Yamanaka ,
K. Higashitani ,
H. Saito ,
I. Hayashi ,
S. Kohama ,
Y. Matsuda ,
K. Oshima ,
M. Nakaya
.
A 622-Mb/s 8×8 ATM switch chip set with shared multibuffer architecture.
IEEE J. Solid-State Circuits
,
7 ,
808 -
815
-
5)
-
J.S. Turner
.
Design of a broadcast packet switching network.
IEEE Trans.
,
6 ,
734 -
743
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19981470
Related content
content/journals/10.1049/el_19981470
pub_keyword,iet_inspecKeyword,pub_concept
6
6