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A two-phase back-bias (VBB) generator is proposed for use in gigabit DRAMs using triple-well CMOS technology. The lower limit of VCC for the proposed VBB generator is a single VT (threshold voltage), whereas that for the conventional VBB generator is 2·VT.
Inspec keywords: pulse generators; CMOS memory circuits; DRAM chips
Other keywords:
Subjects: Pulse generators; Memory circuits; Semiconductor storage; CMOS integrated circuits