A two-phase back-bias (VBB) generator is proposed for use in gigabit DRAMs using triple-well CMOS technology. The lower limit of VCC for the proposed VBB generator is a single VT (threshold voltage), whereas that for the conventional VBB generator is 2·VT.
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http://iet.metastore.ingenta.com/content/journals/10.1049/el_19981332
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content/journals/10.1049/el_19981332
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