Two-phase back-bias generator for low-voltage gigabit DRAMs

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Two-phase back-bias generator for low-voltage gigabit DRAMs

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A two-phase back-bias (VBB) generator is proposed for use in gigabit DRAMs using triple-well CMOS technology. The lower limit of VCC for the proposed VBB generator is a single VT (threshold voltage), whereas that for the conventional VBB generator is 2·VT.

Inspec keywords: pulse generators; CMOS memory circuits; DRAM chips

Other keywords: triple-well CMOS technology; threshold voltage; low-voltage gigabit DRAMs; two-phase back-bias generator

Subjects: Pulse generators; Memory circuits; Semiconductor storage; CMOS integrated circuits

References

    1. 1)
      • Y.H. Kim , J.Y. Sim , H.J. Park , J.I. Doh , K.W. Park , H.W. Chung , J.J. Oh , C.S. Oh , S.H. Ahn . Analysis and prevention of DRAM latch-up during power-on. IEEE J. Solid-State Circuits , 1 , 79 - 85
    2. 2)
      • Y. Tsukikawa , T. Kajimoto , Y. Okasaka , Y. Morooka , K. Furutani , H. Miyamoto , H. Ozaki . An efficient back-bias generator with hybrid pumping circuit for 1.5V DRAMs. IEEE J. Solid-State Circuits , 4 , 534 - 538
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19981332
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