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Finite field division based on recursive division algorithm and composite fields

Finite field division based on recursive division algorithm and composite fields

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A new division scheme for GF(2m) is presented This scheme is based on the recursive division algorithm and composite fields ofthe form GF(22n) (m = 2n). The new division scheme offers reduced time complexity ofapproximately O(2n) when compared to traditional bit-serial architectures with O(22n). The scheme also offers lower hardware requirements when compared to bit-parallel architectures. The circuit architecture presented supports implementation in VLSI systems due to its regular and hardware efficient structures and is therefore suited to the implementation of Reed-Solomon codecs.

Inspec keywords: codecs; computational complexity; digital arithmetic; Reed-Solomon codes; VLSI; integrated logic circuits; dividing circuits

Other keywords: circuit architecture; composite fields; time complexity reduction; finite field division; recursive division algorithm; VLSI systems; Reed-Solomon codecs

Subjects: Logic circuits; Logic and switching circuits; Digital arithmetic methods; Codes; Computational complexity

References

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      • C. Paar . A new architecture for a parallel finite field multiplier with low complexitybased on composite fields. IEEE Trans. Comput. , 7 , 856 - 861
    2. 2)
      • S.J. Fenn , D. Taylor , Benaissa . Division over GF(2m). Electron. Lett. , 2259 - 2261
    3. 3)
      • R. Lidl , H. Niederreiter . (1986) An introduction to finite fields and their applications.
    4. 4)
      • Furness, R., Fenn, S.T.J., Benaissa, M.: `Semi-bit-serial architectures over finite fields for the design of RScodecs', Proc. 1st Int. Symp. on Communication Systems and Digital SignalProcessing, April 1998, Sheffield, p. 125–128.
    5. 5)
      • S.T.J. Fenn , M. Benaissa , D. Taylor . Improved algorithm for division over GF(2m). Electron. Lett. , 469 - 470
    6. 6)
      • Furness, R., Benaissa, M., Fenn, S.T.J.: `Generalised triangular basis multipliers for the design of Reed-Solomoncodecs', Proc. IEEE Workshop on Signal Processing Systems, November 1997, Leicester, p. 202–211.
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